1. Field of the Invention
The present invention relates to a synchronization (sync) signal detection circuit and method for generating a sync signal in a digital television receiver.
2. Description of the Related Art
In the digital television (DTV) field, research is underway into developing robust DTV receivers and digital set-top boxes. As a result, the Advanced Television SubCommittee (ATSC), which is an industry organization which sets standards for DTV components, has specified a vestigial side band (VSB) signal necessary for transmission of a DTV signal.
Reception of a terrestrial broadcast signal, which is a VSB signal with a carrier, is difficult for a multi-path DTV receiver. This difficulty leads to the desire for a robust multi-path receiving system capable of receiving terrestrial broadcast signals. To receive VSB signals, the system should exactly receive a field synchronization (sync) signal or a segment sync signal.
FIG. 1 illustrates the structure of a prior art VSB data frame that is transmitted to a DTV. FIG. 2 illustrates a detailed structure of a prior art field sync signal that is shown in FIG. 1.
Referring to FIG. 1, the VSB data frame consists of two fields (Data+FEC). Each field includes 313 segments, with a first segment corresponding to a field sync signal, shown as Field sync #1 and Field synch #2. The field sync signal contains a total 832 symbols, with the first four symbols corresponding to a segment sync signal generated at levels of +5, −5, −5, and +5.
The segment sync signal indicates the beginning of each of the segments. The field sync signal this includes 828 symbols, excluding the first four symbols corresponding to the segment sync signal, for a total of 832 symbols.
The field sync signal indicates a beginning point of a data field containing data and a forward error correction (FEC), shown as Data+FEC. The field sync signal used both as a reference signal in a channel equalizer, and when determining whether an NTSC rejection filter (NRF) is required. Further, the field sync signal can be used in determining channel characteristics and loop parameters for a phase tracker.
As shown in FIG. 2, the field sync signal includes a plurality of sequences, such as a pseudo-random number (PN) 511 sequence, three PN 63 sequences, a VSB mode sequence, and a reserved sequence. The PN511 sequence is 511 symbols long and used as a training sequence for a channel equalizer.
Like the PN 511 sequence, each of the PN 63 sequences may also be used as a training sequence for a channel equalizer. The sign of the second PN sequence of the three PN 63 sequences changes whenever a field changes, thereby indicating whether a field is the first or second field of the data frame.
The VSB mode sequence is a 24 symbol-length sequence that represents a transmission mode of data currently being transmitted. That is, the VSB mode sequence indicates whether data is transmitted according to a 15-VSB transmission standard, or according to an 8-VSB transmission standard. The reserved sequence is a reserved sequence space that is 104 symbols long.
FIG. 3 is a block diagram of a prior art DTV receiver 300. Referring to FIG. 3, data (DATA) received by the DTV receiver 300 passes through an analog-to-digital converter (ADC) 310 to be converted into digital data. The converted digital data is input to a demodulator 320 where it is demodulated into a demodulated digital signal.
The demodulated digital signal output from the demodulator 320 is input to a phase tracking loop (PTL) 350 via an NRF 330 and an equalizer 340. The digital signal output from the PTL 350 passes through a forward error correction (FEC) unit 360 and is output from the DTV receiver 300. A sync signal detection circuit 370 detects sync signals from either a first data signal (DATA1), which is input from the demodulator 320, or from a second data signal (DATA2), which is input from the PTL 350, as shown in FIG. 3.
FIG. 4 is a block diagram of the sync signal detection circuit 370 of FIG. 3. FIG. 5 is a timing diagram illustrating sync signals output from the sync signal detection circuit 370 of FIG. 3.
Referring to FIG. 4, the DATA1 output from the demodulator 320 of FIG. 3 is applied to a four-symbol sliding correlator 410. The four-symbol sliding correlator 410 performs a correlation operation on every four symbols of the input DATA1 and outputs correlation values to detect the position of the segment sync signal from the input DATA1.
The output correlation values are stored in a buffer 415. The buffer 415 contains the addresses of 832 symbols. The correlation value that corresponds to the location of the segment sync signal is much greater than the other correlation values, and is referred to as the ‘maximum correlation value’.
Accordingly, the address of the maximum correlation value stored in buffer 415 becomes the location of a symbol where generation of the segment sync signals in DATA1 begins. The maximum correlation value is detected by a maximum value detector 420.
The maximum value detector 420 detects and outputs the address of the maximum correlation value stored in buffer 415. In other words, it is possible to determine the location of the symbol where the generation of the segment sync signal in DATA1 begins using the maximum value detector 420. A first counter 425 sets the address of the symbol in which the maximum correlation value is obtained to 0 and starts counting symbols.
After counting all 832 symbols, the first counter 425 is reset to 0. Since one segment consists of 832 symbols, the first counter 425 estimates the position of a generated segment sync signal after the segment sync signal is detected by the maximum value detector 420.
FIG. 5(A) illustrates field sync signals respectively generated for each field. FIG. 5(B) shows the timing diagram of segment sync signals. In FIG. 5(B), the beginning locations of the segment sync signals are illustrated by one-bit signals. As 313 segment sync signals exist in one field, 313 one-bit signals should thus be illustrated in FIG. 5(B). However, only a few of the 313 one-bit signals are illustrated for purposes of convenience.
When the position of the segment sync signal is determined, a PN511 correlator 430 and a PN63 correlator 450 operate to output correlation values. The PN511 correlator 430 performs a correlation operation and outputs a correlation value for each segment. A comparator 435 receives the correlation values from the PN 511 correlator 430 and compares them to a given threshold. The given threshold is a correlation value corresponding to a field sync signal.
If a correlation value output from the PN511 correlator 430 is greater than the given threshold, the position of a symbol corresponding to the correlation value becomes the position of the field sync signal. Like the first counter 425, a second counter 440 sets the position of the symbol corresponding to a correlation value that is greater than the threshold to 0 and begins counting segments.
For example, the second counter 440 counts the segments that are input to the PN511 correlator 430 and is reset to 0 after counting 313 segments. Since one field consists of 313 segments, once the 313 segments for one field have been counted, the second counter 440 estimates the position of a next field sync signal output from the comparator 435.
The PN63 correlator 450 also performs correlation operations and outputs correlation values. A sign generator 455 generates a signal for changing the sign of the field sync signal based on the correlation values output from the PN 63 correlator 450, whenever the field changes.
A field sync signal generator 445 receives information regarding the position of the field sync signal from the second counter 440 and information regarding the sign of the field sync signal from the sign generator 455 and generates the field sync signal based on the received information. In addition to the field sync signal, the field sync signal generator 445 generates sync signals with different timing characteristics.
FIG. 5(C) illustrates field sync signals respectively generated per fields. Here, initial locations of the field sync signals are indicated by one-bit signals. FIG. 5(D) shows signals output from the sign generator 455, each signal carrying information regarding the sign of a field sync signal. The signs of the field sync signals change whenever the fields change.
As described above, the prior art sync signal detection circuit 370 first determines the position of a segment sync signal, and then detects the position of a field sync signal based on the position of the segment sync signal. In general, the sync signal detection circuit 370 operates well under good channel environments such as Gaussian channel environments or Grand Alliance Ensembles channel environments. However, it is difficult for the prior art sync signal detection circuit 370 to detect the position of a segment sync signal under different channel environments of a Brazil channel. In the field of DTV, a Brazil channel is a complicated channel having various signal transmitting passes, making it difficult to detect position of a segment sync signal, for example. Accordingly, in this case, the DTV receiver 300 cannot detect a sync signal with the sync signal detection circuit 370.